GATE | GATE-CS-2005 | Question 80

Consider the following data path of a CPU. The, ALU, the bus and all the registers in the data path are of identical size. All operations including incrementation of the PC and the GPRs are to be carried out in the ALU. Two clock cycles are needed for memory read operation - the first one for loading address in the MAR and the next one for loading data from the memory bus into the MDR 79. The instruction "call Rn, sub" is a two word instruction. Assuming that PC is incremented during the fetch cycle of the first word of the instruction, its register transfer interpretation is

Rn < = PC + 1;
PC < = M[PC]; 

The minimum number of CPU clock cycles needed during the execution cycle of this instruction is: